Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes.

2018-12-05 17:10:11 -08:00

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golden

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00_code_format_check_test.py

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01_library_drc_test.py

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02_library_lvs_test.py

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03_contact_test.py

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03_path_test.py

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03_ptx_1finger_nmos_test.py

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03_ptx_1finger_pmos_test.py

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03_ptx_3finger_nmos_test.py

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03_ptx_3finger_pmos_test.py

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03_ptx_4finger_nmos_test.py

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03_ptx_4finger_pmos_test.py

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03_wire_test.py

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04_pand2_test.py

Add pand2 draft

2018-11-26 13:45:22 -08:00

04_pbitcell_test.py

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04_pbuf_test.py

Add pand2 draft

2018-11-26 13:45:22 -08:00

04_pinv_1x_beta_test.py

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04_pinv_1x_test.py

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04_pinv_2x_test.py

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04_pinv_10x_test.py

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04_pinvbuf_test.py

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04_pnand2_test.py

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04_pnand3_test.py

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04_pnor2_test.py

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04_precharge_test.py

precharge bl is on metal2 only. simplify via position code.

2018-11-09 09:11:00 -08:00

04_replica_pbitcell_test.py

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04_single_level_column_mux_test.py

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05_bitcell_1rw_1r_array_test.py

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05_bitcell_array_test.py

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05_pbitcell_array_test.py

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06_hierarchical_decoder_test.py

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06_hierarchical_predecode2x4_test.py

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06_hierarchical_predecode3x8_test.py

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07_single_level_column_mux_array_test.py

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08_precharge_array_test.py

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08_wordline_driver_test.py

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09_sense_amp_array_test.py

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10_write_driver_array_test.py

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11_dff_array_test.py

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11_dff_buf_array_test.py

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11_dff_buf_test.py

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12_tri_gate_array_test.py

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13_delay_chain_test.py

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14_replica_bitline_multiport_test.py

Changed syntax in replica_bl tests, golden data to fit new values in delay tests.

2018-11-19 16:51:43 -08:00

14_replica_bitline_test.py

Changed syntax in replica_bl tests, golden data to fit new values in delay tests.

2018-11-19 16:51:43 -08:00

16_control_logic_test.py

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19_bank_select_test.py

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19_multi_bank_test.py

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19_pmulti_bank_test.py

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19_psingle_bank_test.py

Clean up psingle_bank_test

2018-11-09 09:34:34 -08:00

19_single_bank_1rw_1r_test.py

Add multiport bank test

2018-11-13 16:06:21 -08:00

19_single_bank_test.py

Clean up psingle_bank_test

2018-11-09 09:34:34 -08:00

20_psram_1bank_2mux_1rw_1w_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_psram_1bank_2mux_1w_1r_test.py

Remove extra rotated vias in bitcell array to simplify power routing

2018-11-29 18:13:15 -08:00

20_psram_1bank_2mux_test.py

Skip failing tests with comments for bugs.

2018-11-30 12:33:43 -08:00

20_psram_1bank_4mux_1rw_1r_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_2mux_1rw_1r_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_2mux_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_4mux_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_8mux_1rw_1r_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_8mux_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_nomux_1rw_1r_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_1bank_nomux_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

20_sram_2bank_test.py

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21_hspice_delay_test.py

Fixed delay test values.

2018-12-05 00:13:23 -08:00

21_hspice_setuphold_test.py

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21_ngspice_delay_test.py

Fixed delay test values.

2018-12-05 00:13:23 -08:00

21_ngspice_setuphold_test.py

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22_psram_1bank_2mux_func_test.py

Changed s_en delay calculation based recent control logic changes.

2018-12-05 17:10:11 -08:00

22_psram_1bank_4mux_func_test.py

Changed s_en delay calculation based recent control logic changes.

2018-12-05 17:10:11 -08:00

22_psram_1bank_8mux_func_test.py

Update unit test golden results. Skip two tests.

2018-11-29 17:28:57 -08:00

22_psram_1bank_nomux_func_test.py

Add more layout and functional port tests.

2018-11-29 10:28:43 -08:00

22_sram_1bank_2mux_func_test.py

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22_sram_1bank_4mux_func_test.py

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22_sram_1bank_8mux_func_test.py

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22_sram_1bank_nomux_func_test.py

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22_sram_1rw_1r_1bank_nomux_func_test.py

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23_lib_sram_model_test.py

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23_lib_sram_prune_test.py

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23_lib_sram_test.py

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24_lef_sram_test.py

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25_verilog_sram_test.py

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26_pex_test.py

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27_worst_case_delay_test.py

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30_openram_test.py

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config_20_freepdk45.py

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config_20_scn3me_subm.py

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config_20_scn4m_subm.py

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regress.py

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testutils.py

Comment out regress CI debug code

2018-11-10 13:44:36 -08:00