OpenRAM/compiler
Jesse Cirimelli-Low 0034798787 both rbl replica array working 2023-09-11 11:23:39 -07:00
..
base single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
characterizer Force to use bash for simulators 2023-08-10 16:05:24 -07:00
datasheet Update copyright year 2023-01-28 22:56:27 -08:00
drc Update copyright year 2023-01-28 22:56:27 -08:00
gdsMill Use library imports globally 2022-11-27 13:01:20 -08:00
model_configs Update copyright year 2023-01-28 22:56:27 -08:00
modules both rbl replica array working 2023-09-11 11:23:39 -07:00
router copy router from dev 2023-09-03 13:16:18 -07:00
tests singleport bitcell array laying out 2023-08-21 19:24:06 -07:00
verify Fix newline for scripts 2023-01-28 22:59:08 -08:00
Makefile Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
debug.py Update copyright year 2023-01-28 22:56:27 -08:00
gen_stimulus.py Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
globals.py Add optional $CONDA_HOME environment variable 2023-05-11 16:42:29 -07:00
model_data_util.py Update copyright year 2023-01-28 22:56:27 -08:00
options.py Change OPTS.route_supplies option since there's only one router now 2023-08-02 21:48:29 -07:00
rom.py Fixed formatting on all files 2023-06-14 12:28:36 -07:00
rom_config.py ROM binary file support 2023-04-03 16:04:12 -07:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram.py functional should use full sp file path 2023-05-23 10:58:43 -07:00
sram_config.py Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
sram_factory.py Update copyright year 2023-01-28 22:56:27 -08:00
view_profile.py Update copyright year 2023-01-28 22:56:27 -08:00