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OpenRAM
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3,960 Commits 4 Branches 63 Tags 78 MiB
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20 Commits

Author SHA1 Message Date
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg fbb2ea5fb6 Intersection now returns a pin_layout fixed during LEF computation. 2022-05-13 13:56:16 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg 8bf37ca708 Connect dnwell taps to gnd 2021-05-26 17:38:09 -07:00
mrg 2243761500 Must transitively cut blockages until no more. 2021-05-05 13:44:06 -07:00
mrg a111ecb74c Fix extra indent that made openlane fail. 2021-04-22 13:05:51 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
jsowash 3bd69d2759 Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00