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OpenRAM
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31 Commits

Author SHA1 Message Date
mrg c69eb47a7a Finalize uniquify option for SRAMs 2021-06-22 16:13:33 -07:00
Jesse Cirimelli-Low e775f7a355 fixed indent 2021-06-16 12:36:00 -07:00
Jesse Cirimelli-Low 2b9df2ff1f uncomment function sim and datasheet generation 2021-06-16 11:23:27 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg 0a02f635ad Remove lvs_write from sram 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
Hunter Nichols c7f14b1bf9 Removed stale fixme and moved words per row OPTS setting. 2021-02-15 15:20:32 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 1885794016 Only write drc/lvs scripts if drc/lvs is enabled 2020-12-23 07:16:43 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 57e708a6e1 Add 200 cycles. Can be commented out or run for shorter. 2020-11-09 15:20:36 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
Hunter Nichols 12a8531248 Allowed for OPTS writeback of words_per_row if automatically generated during generation. 2020-10-21 03:02:39 -07:00
mrg c2629edc1b Allow 16-way column mux 2020-10-06 16:27:02 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
mrg c8c74e8b69 Fix lvs_write in sram class 2020-04-06 15:20:59 -07:00
mrg 6506622dfb PEP8 Formatting 2020-03-05 16:20:21 -08:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash 67c6cdf3bb Fixed error where word_size was compared to num_words and added write_size to control_logic.py 2019-07-01 15:51:40 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
mrg bf86969972 Create sram subdirectory. 2019-05-31 08:56:24 -07:00