17 Commits

Author	SHA1	Message	Date
Hunter Nichols	2ce7323838	Removed all unused analytical delay functions.	2019-08-06 17:09:25 -07:00
Matt Guthaus	6e044b776f	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
mrg	fc12ea24e9	Add boundary to every module and pgate for visual debug.	2019-06-03 15:27:37 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	0e96648211	Added linear corner factors in analytical delay model.	2019-03-04 00:42:18 -08:00
Matt Guthaus	a418431a42	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
Matt Guthaus	a2a9cea37e	Make column decoder same height as control to control and supply overlaps	2018-11-28 16:59:58 -08:00
Matt Guthaus	aa779a7f82	Initial two port bank in SCMOS	2018-11-13 16:05:22 -08:00
Matt Guthaus	e22e658090	Converted all submodules to use _bit notation instead of [bit]	2018-10-11 09:53:08 -07:00
Matt Guthaus	8664f7a0b8	Converted all modules to not run create_layout when netlist_only ... mode is enabled.	2018-08-27 16:42:48 -07:00
Matt Guthaus	138a70fc23	Add place_inst routine. ... Separate create netlist and layout in some modules.	2018-08-27 10:42:40 -07:00
Hunter Nichols	d0e6dc9ce7	First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.	2018-02-26 16:32:28 -08:00
Hunter Nichols	62ad30e741	Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate.	2018-02-22 19:35:54 -08:00
Hunter Nichols	8ea384a761	Fixed merging issues with power branch	2018-02-14 15:21:42 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00