luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
Code Issues Packages Projects Releases Wiki Activity
997 Commits 5 Branches 63 Tags
e60deddfeabc23dca242f8d69a7559c1ce75fdab
Commit Graph
3 Commits
Author SHA1 Message Date
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00