12 Commits

Author	SHA1	Message	Date
Bastian Koppelmann	f9babcf666	port_data: Each submodule now specifies their bl/br names ... before the names of bl/br from the bitcell were assumed. If we want to allow renaming of bl/br from bitcells, we have to seperate the other modules from that. Note, that we don't touch every occurence of bl/br, but only the once necessary that pin renaming of the bitcell works. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>	2020-02-12 15:00:50 +01:00
jcirimel	b212b3e85a	s8 gdsless netlist only working up to dff array	2020-02-09 21:37:09 -08:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Hunter Nichols	d54074d68e	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Matt Guthaus	b58fd03083	Change pbuf/pinv to pdriver in control logic.	2019-01-23 12:03:52 -08:00
Matt Guthaus	1fe767343e	Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.	2018-11-07 11:31:44 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00