OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	ce8c2d983d	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00
Matt Guthaus	4932d83afc	Add design rules classes for complex design rules	2018-10-12 09:44:36 -07:00
Michael Timothy Grimes	27427d4192	Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.	2018-09-09 22:06:29 -07:00
Matt Guthaus	6963a1092f	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Matt Guthaus	19d46f5954	Finalized separation of netlist/layout creation.	2018-08-27 14:18:32 -07:00
Matt Guthaus	69921b0844	Add enclosing well to column mux. Move well contact to cell boundary.	2018-06-29 11:35:29 -07:00
Michael Timothy Grimes	8f131ddb2f	commiting changes from most recent pull from dev	2018-05-22 17:30:51 -07:00
Michael Timothy Grimes	766042fe69	changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit	2018-05-22 14:16:51 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
Matt Guthaus	a6c2e77bcf	Move precharge and column mux cells to pgate directory. Move gnd to M3 in column mux. Create column mux cell unit test.	2018-04-06 17:15:14 -07:00

11 Commits