17 Commits

Author	SHA1	Message	Date
SWalker	ce1861f342	proper output rom bank output layer	2023-10-31 23:24:21 -07:00
SWalker	9b99e6c124	bunch of cleanups to core rom classes	2023-10-31 23:24:21 -07:00
SWalker	3271c5e73c	fixing drc on rom bank, mostly spacing tweaks	2023-10-31 23:24:21 -07:00
Eren Dogan	f8b2c1e9b9	Change OPTS.route_supplies option since there's only one router now	2023-08-02 21:48:29 -07:00
Eren Dogan	54fc34392d	Remove unnecessary imports	2023-08-02 21:28:21 -07:00
Eren Dogan	87eca6b7db	Use the initial bbox to route supply and signals	2023-08-02 18:01:09 -07:00
Eren Dogan	5b0f97860a	Calculate bbox inside the router	2023-08-02 09:30:50 -07:00
Eren Dogan	877f20e071	Use the new routers in ROMs	2023-08-01 19:10:02 -07:00
Gary Mejia	692acd2066	Verilog ROM model created for testing	2023-06-12 15:35:54 -07:00
Jacob Walker	52791a2719	a space	2023-03-30 11:30:50 -07:00
Jacob Walker	c1fb3cab6c	1kb rom DRC clean	2023-03-30 11:30:50 -07:00
Jacob Walker	fef9902c45	rom base passing tests with top level routing	2023-03-30 11:30:50 -07:00
Jacob Walker	4c34a54d32	top level boundary fixes	2023-03-30 11:30:50 -07:00
Jacob Walker	7fe5ed5c41	edge routing	2023-03-30 11:30:50 -07:00
Jacob Walker	09f9c4cc20	some rom bank cleanup	2023-03-30 11:30:50 -07:00
mrg	56e14113aa	Change rom_base_bank name and top pin names	2023-03-30 11:30:50 -07:00
mrg	fe65a20431	Rename ROM unit tests.	2023-03-30 11:30:50 -07:00