OpenRAM

mirror of https://github.com/VLSIDA/OpenRAM.git

Author	SHA1	Message	Date
Jesse Cirimelli-Low	038acd1568	single port rba lvs progress	2022-03-07 01:20:59 -08:00
Jesse Cirimelli-Low	8d9166a01b	only rba lvs errors is colend body extraction	2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low	8a0450afac	adjust replica col wls	2021-12-22 15:46:03 -08:00
Jesse Cirimelli-Low	8879820af4	replica col lvs fix	2021-12-15 14:19:52 -08:00
mrg	fa2232fc11	Initial commit of sky130 config files	2021-10-04 15:16:28 -07:00