d2ca2efdbe
Limit ps, pd, as, ad precision in ptx.
2018-11-28 09:47:54 -08:00
ce8c2d983d
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
4932d83afc
Add design rules classes for complex design rules
2018-10-12 09:44:36 -07:00
42719b8ec2
Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.
2018-09-12 01:53:41 -07:00
8664f7a0b8
Converted all modules to not run create_layout when netlist_only
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mode is enabled.
2018-08-27 16:42:48 -07:00
19d46f5954
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
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Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
97c08bce95
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
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Shift s_en buffers even with other cells.
2018-03-23 08:14:09 -07:00
7100d6f904
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
Matt Guthaus
Matt Guthaus
Michael Timothy Grimes