OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	e22e658090	Converted all submodules to use _bit notation instead of [bit]	2018-10-11 09:53:08 -07:00
Matt Guthaus	6963a1092f	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
Michael Timothy Grimes	f3cca7eea0	Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases.	2018-08-31 23:28:06 -07:00
Matt Guthaus	e17c69be3e	Clean up new code for add_modules, add_pins and netlist/layouts.	2018-08-28 10:24:09 -07:00
Matt Guthaus	6401cbf2a6	Move place function to instance class rather than hierarchy.	2018-08-27 17:25:39 -07:00
Matt Guthaus	0daad338e4	All modules have split netlist/layout.	2018-08-27 11:13:34 -07:00
Matt Guthaus	f34c4eb7dc	Convert entire OpenRAM to use python3. Works with Python 3.6. Major changes: Remove mpmath library and use numpy instead. Convert bytes to new bytearrays. Fix class name check for duplicate gds instances. Add explicit integer conversion from floats. Fix importlib reload from importlib library Fix new key/index syntax issues. Fix filter and map conversion to lists. Fix deprecation warnings. Fix Circuits vs Netlist in Magic LVS results. Fix file closing warnings.	2018-05-14 16:15:45 -07:00
Matt Guthaus	63a8f7c653	Remove m2 from write driver	2018-04-16 16:15:35 -07:00
Matt Guthaus	4f8ab78ee2	Change write driver supply pins to M2	2018-04-11 09:29:54 -07:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00

10 Commits