16 Commits

Author	SHA1	Message	Date
Hunter Nichols	24b1fa38a0	Added graph fixes to handmade multiport cells.	2019-07-30 20:31:32 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	043018e8ba	Functional tests working with new RBL.	2019-07-12 08:42:36 -07:00
Hunter Nichols	4e08e2da87	Merged and fixed conflicts with dev	2019-06-25 16:55:50 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
Hunter Nichols	ad229b1504	Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking.	2019-05-28 16:55:09 -07:00
Hunter Nichols	d08181455c	Added multiport bitcell support for storage node checks	2019-05-20 22:50:03 -07:00
Hunter Nichols	d8617acff2	Merged with dev	2019-05-15 18:48:00 -07:00
Hunter Nichols	d54074d68e	Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.	2019-05-07 00:52:27 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Hunter Nichols	e292767166	Added graph creation and functions in base class and lower level modules.	2019-04-24 14:23:22 -07:00
Hunter Nichols	a500d7ee3d	Adjusted bitcell analytical delays for multiport cells.	2019-04-09 02:49:52 -07:00
Hunter Nichols	80a325fe32	Added corner information for analytical power estimation.	2019-03-04 19:27:53 -08:00
Hunter Nichols	0e96648211	Added linear corner factors in analytical delay model.	2019-03-04 00:42:18 -08:00
Matt Guthaus	6cdc870091	Copy 1rw/1r cell to 1w/1r.	2019-02-24 09:54:45 -08:00