7 Commits

Author	SHA1	Message	Date
mrg	a0e263b14a	Add vdd/gnd pins to the side.	2021-05-03 15:14:15 -07:00
mrg	6cfa20731c	Consistent naming in example configs	2020-11-18 09:59:38 -08:00
mrg	bd9bac6635	Fixed nominal_corner_only parameter.	2020-10-30 15:52:07 -07:00
Matt Guthaus	0cdd3af1aa	Change default nominal corners to false and enable in test config.	2019-11-29 12:08:53 -08:00
Matt Guthaus	84c7146792	Fix some pep8 errors/warnings in pgate and examples.	2019-10-06 17:30:16 +00:00
Matt Guthaus	74f904a509	Cleanup options for front-end. Improve info output.	2019-04-01 10:35:17 -07:00
Matt Guthaus	5de7ff3773	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00