9 Commits

Author	SHA1	Message	Date
Matt Guthaus	0daad338e4	All modules have split netlist/layout.	2018-08-27 11:13:34 -07:00
Matt Guthaus	00a87d57ab	Modified pinvbuf to have a stage effort of 4 for driving the ... clock bar to wordline enable. Fixed comments in stimulus file to have right cycle numbers. Removed clock gating on we signal since clock gating is already done on the WL signals. It is redundant.	2018-07-26 11:28:48 -07:00
Matt Guthaus	e038561b4a	Move supply to M3 in wordline driver	2018-04-11 16:23:45 -07:00
Matt Guthaus	97c08bce95	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. ... Shift s_en buffers even with other cells.	2018-03-23 08:14:09 -07:00
Matt Guthaus	bab92fcf38	Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.	2018-03-23 08:13:20 -07:00
Hunter Nichols	d0e6dc9ce7	First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.	2018-02-26 16:32:28 -08:00
Hunter Nichols	62ad30e741	Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate.	2018-02-22 19:35:54 -08:00
Hunter Nichols	8ea384a761	Fixed merging issues with power branch	2018-02-14 15:21:42 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00