8 Commits

Author	SHA1	Message	Date
Matt Guthaus	512448f9e8	Fix pin names to lower case. Fix write driver DRC errors and LVS error.	2018-01-31 17:37:16 -08:00
Matt Guthaus	490a70dee9	Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.	2018-01-19 16:38:19 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	3ea003c367	Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.	2017-09-11 14:30:52 -07:00
Matt Guthaus	d17711c394	Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way.	2017-08-24 16:22:14 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
mguthaus	e92cb9ecef	Removed array_type from ms_flop_array since it is extraneous code.	2017-07-03 12:08:50 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00