12 Commits

Include renames

Author	SHA1	Message	Date
Matt Guthaus	8d9b79dfd8	Add dff_buf for buffered flop arrays.	2018-03-04 16:13:10 -08:00
mguthaus	1297cb4e40	Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell.	2018-02-16 10:40:05 -08:00
Matt Guthaus	bab9ae8201	Fix off-grid pin and overlap problems for pins in freepdk dff cell.	2018-02-15 17:54:26 -08:00
Matt Guthaus	e66a37c916	Put DFF pins on 2.5nm grid in 45nm.	2018-02-15 11:08:57 -08:00
Matt Guthaus	2d3acb03a1	Add bbox for dff in freepdk45	2018-02-14 17:04:31 -08:00
Matt Guthaus	d89e49aecc	Add metal2 pins to freepdk45 dff.	2018-02-14 16:58:41 -08:00
Matt Guthaus	0804a1eceb	Add new DFF. Create DFF module. Start dff_array, not tested.	2018-02-14 15:16:28 -08:00
Matt Guthaus	512448f9e8	Fix pin names to lower case. Fix write driver DRC errors and LVS error.	2018-01-31 17:37:16 -08:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	d17711c394	Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way.	2017-08-24 16:22:14 -07:00
Matt Guthaus	cf940fb15d	Development version of new pin data structure. Tests pass LVS/DRC except for bank level.	2017-08-23 15:02:15 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00