11 Commits

Author	SHA1	Message	Date
Aditi Sinha	a5c211bd90	Merge branch 'dev' into bisr	2020-05-13 22:39:29 +00:00
mrg	b7c66d7e07	Changes to simplify metal preferred directions and pitches. ... Changes to allow decoder height to be a 2x multiple of bitcell height. Split of control logic tests. Fixed track spacing in SRAM and channel router PEP8 cleanup.	2020-05-10 11:32:45 -07:00
Aditi Sinha	2498ff07ea	Merge branch 'dev' into bisr	2020-05-02 07:48:35 +00:00
mrg	58fbc5351a	Change rows to outputs in hierarchical decoder	2020-04-08 17:05:16 -07:00
Aditi Sinha	34939ebd70	Merge branch 'dev' into bisr	2020-02-20 17:09:09 +00:00
mrg	9beb0f4ece	Add separate well design rules. ... Needed to fix various pgates with wells. Did some cleanup of these gates as well.	2020-01-23 19:43:41 +00:00
Matt Guthaus	ed28b4983b	Clean up and generalize layer rules. ... Convert metalN to mN. Generalize helper constants in modules for space, width, enclose, etc. Use layer stacks whever possible. Try to remove drc() calls in liu of helper constants.	2019-12-17 11:03:36 -08:00
Aditi Sinha	5b3846e1e5	Changed replica bitcell array to work with bank tests for non power of two rows	2019-12-08 13:24:39 +00:00
mrg	f542613d78	Correct wordline_driver enable to en, not en_bar.	2019-07-05 10:31:05 -07:00
mrg	bfe4213fce	Port address added to entire SRAM.	2019-07-05 09:44:42 -07:00
mrg	4c6556f1bc	Add port address module	2019-07-05 09:04:48 -07:00