8 Commits

Author	SHA1	Message	Date
Matthew Guthaus	8f473b26a9	Add replica bitcell test for 1 port	2019-12-05 01:14:06 +00:00
Matt Guthaus	864639d96e	Remove old replica bitline.	2019-07-18 15:19:40 -07:00
mrg	e550d6ff10	Port name maps between bank and replica array working.	2019-07-15 11:29:29 -07:00
mrg	b841fd7ce3	Replica bitcell array with arbitrary RBLs working	2019-07-10 15:56:51 -07:00
mrg	b9d993c88b	Add dummy bitcell module. ... Modify bitcell logic to guess if bitcell is not "bitcell" No longer need to specify replica (and dummy) bitcell explicitly Add support for 1 or 2 port replica array.	2019-07-05 12:58:52 -07:00
Matt Guthaus	f914ab0ece	Re-enable replica tests	2019-07-03 14:57:47 -07:00
mrg	bc4a3ee2b7	New port_data module works in SCMOS	2019-07-03 13:17:12 -07:00
mrg	4523a7b9f6	Replica bitcell array working	2019-06-19 16:03:21 -07:00