13 Commits

Author	SHA1	Message	Date
Matt Guthaus	37b81c0af1	Remove options from example config files	2018-11-05 12:47:47 -08:00
Hunter Nichols	da1b003d10	Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes.	2018-10-24 00:17:08 -07:00
Hunter Nichols	016604f846	Fixed spacing in golden lib files. Added column mux into analytical model.	2018-10-24 00:16:26 -07:00
Hunter Nichols	53cb4e7f5e	Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working.	2018-10-22 23:33:01 -07:00
Michael Timothy Grimes	a27cdb4fbc	Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport	2018-10-17 07:32:03 -07:00
Matt Guthaus	5e9fe65907	Remove banks from example configs	2018-10-12 10:23:34 -07:00
Hunter Nichols	7b4e001885	Altered web to only be generated for rw ports.	2018-10-04 15:08:12 -07:00
Hunter Nichols	371a57339f	Fixed bugs to allow characterization of multiple read ports. Improved some debug messages.	2018-10-04 14:09:09 -07:00
Hunter Nichols	c876bbfe73	Changed characterizer control generation to match recent changes in multiport.	2018-10-04 14:09:09 -07:00
Hunter Nichols	2e322be7f7	Added changes the control logic PWL generation to match changes made in stimuli.	2018-10-04 14:09:09 -07:00
Hunter Nichols	88f2238e03	Multiport variable bug fix and removed unused code.	2018-10-04 14:09:09 -07:00
Hunter Nichols	bb79d9a62d	Added regex pattern matching to trim_spice to handle multiport.	2018-10-04 14:09:09 -07:00
Matt Guthaus	2df9b79b28	Remove scn3me lib files. Remove bank references.	2018-09-24 11:28:43 -07:00