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OpenRAM
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19 Commits

Author SHA1 Message Date
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus afcc3563ae Add new supplies to RBL and control logic 2018-07-16 12:58:15 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 3fe4578feb Change stages of delay to odd 2018-04-16 10:15:15 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Hunter Nichols e6d6680da1 Fixed conflict in delay.py 2018-02-27 13:02:22 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
mguthaus 28fe49d069 Change RBL to allow stages and FO for configuration 2018-02-16 11:51:01 -08:00
Matt Guthaus 2e3e95efda Change ratio of delay line and RBL size. Need to tune it better automatically. 2018-02-14 16:50:08 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00