113 Commits

Author	SHA1	Message	Date
Matt Guthaus	97c08bce95	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. ... Shift s_en buffers even with other cells.	2018-03-23 08:14:09 -07:00
Matt Guthaus	1f81b24e96	Single bank passing DRC and LVS again. ... Unfold hierarchical decoder to improve routability.	2018-03-23 08:13:10 -07:00
Matt Guthaus	b867e163a6	Move label pins to center like layout pins. ... Rework of control logic with vertical poly. Passes DRC/LVS. Single bank passing DRC.	2018-03-23 08:12:59 -07:00
Matt Guthaus	ed8eaed54f	Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.	2018-03-23 08:12:47 -07:00
Hunter Nichols	e6d6680da1	Fixed conflict in delay.py	2018-02-27 13:02:22 -08:00
Hunter Nichols	d0e6dc9ce7	First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.	2018-02-26 16:32:28 -08:00
Hunter Nichols	beb7dad9bc	Added corner paramters to power functions. This commit does not compile (sorry)	2018-02-22 00:15:55 -08:00
Hunter Nichols	d4a0f48d4f	Added power calculations for inverter. Still testing.	2018-02-21 19:51:21 -08:00
Hunter Nichols	179a27b0e3	Added some power functions.	2018-02-20 18:22:23 -08:00
mguthaus	28fe49d069	Change RBL to allow stages and FO for configuration	2018-02-16 11:51:01 -08:00
Matt Guthaus	2e3e95efda	Change ratio of delay line and RBL size. Need to tune it better automatically.	2018-02-14 16:50:08 -08:00
mguthaus	767990ca3b	Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name.	2018-02-13 15:54:50 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00