64 Commits

Author	SHA1	Message	Date
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. ... Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
mguthaus	5c10aebc0f	Fix bug in multifinger ptx. Replace LEF file with new snapped layout.	2017-10-06 16:23:23 -07:00
Matt Guthaus	59a0394c2b	Update LEF files with modified blockages.	2017-10-04 20:17:30 -07:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	857b997367	Modify LEF output to have all capital LAYER. Remove extra space before new lines.	2017-08-15 08:21:54 -07:00
Matt Guthaus	d77216d6dd	Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.	2017-08-07 10:24:45 -07:00
Matt Guthaus	7ec20a72c8	Fix old unit test golden result	2017-07-06 14:16:02 -07:00
Matt Guthaus	20d8c0bc45	Improved characterizer.	2017-07-06 08:42:25 -07:00
Matt Guthaus	4e97e385e1	New lib file. Tolerances were off.	2017-06-06 11:06:16 -07:00
mguthaus	f32912f07c	Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.	2017-06-02 11:11:57 -07:00
Matt Guthaus	46c56863ee	Bin Wu fixed unit test to pass with analytical delay option	2017-05-31 08:01:42 -07:00
Matt Guthaus	841532a52f	Change characterizer to be one data structure. Add approximate diff for lib file.	2016-11-23 17:18:48 -08:00
Samira Ataei	d195df682d	Added Power results to lib. ... Fixed min_period and min_pulse_width values. Updated lib golden files.	2016-11-19 20:19:16 -06:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00