OpenRAM

Commit Graph

Author	SHA1	Message	Date
Matt Guthaus	e0a6b59773	Fix LEF test mismatch in regression.	2018-01-12 08:54:31 -08:00
Matt Guthaus	1701eac1a9	Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.	2018-01-11 10:24:44 -08:00
Matt Guthaus	4885616bec	Remove metal3 in LEF library cells.	2017-12-19 13:12:39 -08:00
Matt Guthaus	9a4b2b4341	Revised LEF and Verilog generation. Does not read GDS for speed improvements.	2017-12-19 09:01:24 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
mguthaus	5c10aebc0f	Fix bug in multifinger ptx. Replace LEF file with new snapped layout.	2017-10-06 16:23:23 -07:00
Matt Guthaus	59a0394c2b	Update LEF files with modified blockages.	2017-10-04 20:17:30 -07:00
Matt Guthaus	e06e1691c8	Two bank SRAMs working in both technologies.	2017-09-29 16:22:13 -07:00
Matt Guthaus	857b997367	Modify LEF output to have all capital LAYER. Remove extra space before new lines.	2017-08-15 08:21:54 -07:00
Matt Guthaus	d77216d6dd	Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.	2017-08-07 10:24:45 -07:00
mguthaus	f32912f07c	Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.	2017-06-02 11:11:57 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00

12 Commits