OpenRAM

Author	SHA1	Message	Date
Matt Guthaus	1dc7752429	Fix 6T and replica cell contact spacing issues with Magic DRC. DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again.	2018-01-26 12:39:00 -08:00
Matt Guthaus	abee235963	Rewrite the parameterized transistor and gate classes. Changes propagate through all designs. All modules use instance and layout pins.	2017-12-12 15:04:01 -08:00
Matt Guthaus	88740c107f	Improve global and code structure using modules. Comment and reorganize globals.py Tests consistently use globals module for OPTions. Add characterizer as module support. Modify unit tests to reload new characterizer for ngspice/hspice. Enable relative and absolute config file arguments so you can run openram from anywhere on any config file.	2017-11-16 13:52:58 -08:00
Matt Guthaus	3e0f39cd8e	Skeleton code for indirect DRC/LVS/PEX tools.	2017-11-14 14:59:14 -08:00
Matt Guthaus	d77216d6dd	Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.	2017-08-07 10:24:45 -07:00
mguthaus	f32912f07c	Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.	2017-06-02 11:11:57 -07:00
Matt Guthaus	f48272bde6	RELEASE 1.0	2016-11-08 09:57:35 -08:00