9 Commits

Author	SHA1	Message	Date
Hunter Nichols	4f08062268	Added custom 1rw+1r bitcell. Testing are currently failing.	2018-10-22 17:02:21 -07:00
Hunter Nichols	3ac2d29940	Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation	2018-10-09 17:44:28 -07:00
Hunter Nichols	7b4e001885	Altered web to only be generated for rw ports.	2018-10-04 15:08:12 -07:00
Hunter Nichols	371a57339f	Fixed bugs to allow characterization of multiple read ports. Improved some debug messages.	2018-10-04 14:09:09 -07:00
Hunter Nichols	c876bbfe73	Changed characterizer control generation to match recent changes in multiport.	2018-10-04 14:09:09 -07:00
Hunter Nichols	2e322be7f7	Added changes the control logic PWL generation to match changes made in stimuli.	2018-10-04 14:09:09 -07:00
Hunter Nichols	88f2238e03	Multiport variable bug fix and removed unused code.	2018-10-04 14:09:09 -07:00
Hunter Nichols	bb79d9a62d	Added regex pattern matching to trim_spice to handle multiport.	2018-10-04 14:09:09 -07:00
Matt Guthaus	2df9b79b28	Remove scn3me lib files. Remove bank references.	2018-09-24 11:28:43 -07:00