OpenRAM

Author	SHA1	Message	Date
jsowash	5258016c9f	Changed location of port for din_reg.	2019-07-06 12:27:24 -07:00
jsowash	6fe78fe04a	Removed begin end for Verilog without wmask.	2019-07-06 11:29:34 -07:00
jsowash	24bfaa3b76	Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.	2019-07-05 15:55:03 -07:00
jsowash	ad9193ad5a	Verified 1rw mask writing and changed verilog.py accordingly.	2019-07-05 15:08:59 -07:00
jsowash	125112b562	Added wmask flip flop. Need work on placement still.	2019-07-04 10:34:14 -07:00
Matt Guthaus	a234b0af88	Fix space before comment	2019-06-14 08:43:41 -07:00
Matt Guthaus	0f03553689	Update copyright to correct years.	2019-05-06 06:50:15 -07:00
Matt Guthaus	3f9a987e51	Update copyright. Add header to all OpenRAM files.	2019-04-26 12:33:53 -07:00
Matt Guthaus	20b869f8e1	Remove tabs	2019-01-11 14:16:57 -08:00
Matt Guthaus	5de7ff3773	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
Matt Guthaus	84c798d9e4	Move last few modules to base dir	2018-02-09 10:29:37 -08:00