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36d8d98b177d89b3e0874112f355cd85f8369ee2
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4 Commits
Author SHA1 Message Date
Jesse Cirimelli-Low bfc20a9aa9 removes debug corners 2019-02-07 06:38:07 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Matt Guthaus 82a09be026 Move inspect into if statement for runtime 2019-01-30 08:42:25 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00