8 Commits

Author	SHA1	Message	Date
mrg	927de3a240	Debugging then disabling spare cols functional sim for now.	2021-06-29 15:47:53 -07:00
mrg	b510925bdb	Enable pruning by default (except on unit tests)	2021-04-07 16:08:29 -07:00
mrg	d609e4ea04	Reimplement trim options (except on unit tests). ... Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram.	2021-04-07 16:07:56 -07:00
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	0ba2feee53	Fix errors in new run_sim calls and corners	2020-11-09 13:59:46 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	8e908f016e	PEP8 formatting	2020-09-29 13:43:59 -07:00
Aditi Sinha	eb0c595dbe	SRAM layout and functional tests with spare cols	2020-06-03 12:31:30 +00:00