17 Commits

Author	SHA1	Message	Date
mrg	10542d6cc3	Output DRC and LVS run files to output directory.	2020-11-09 11:12:31 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	c2629edc1b	Allow 16-way column mux	2020-10-06 16:27:02 -07:00
mrg	b32c123dab	PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.	2020-10-01 11:10:18 -07:00
Hunter Nichols	af22e438f1	Added option to output an extended configuration file that includes defaults.	2020-09-08 18:40:39 -07:00
mrg	0bec6f0439	Fix SRAM to use simulation spice instead of LVS spice	2020-08-12 10:41:21 -07:00
Bob Vanhoof	9b8ef5ef57	fix: generated pex file was not passed correctly to lib characterizer	2020-08-03 10:16:12 +02:00
mrg	487027a9f2	Fix pex file names	2020-07-30 11:35:13 -07:00
Bob Vanhoof	ee3da91232	calibrepex: file copy fix	2020-07-15 11:50:21 +02:00
mrg	282f944b2f	Also write .lvs file since it can be different the .sp	2020-07-03 06:55:35 -07:00
mrg	c8c74e8b69	Fix lvs_write in sram class	2020-04-06 15:20:59 -07:00
mrg	6506622dfb	PEP8 Formatting	2020-03-05 16:20:21 -08:00
Matthew Guthaus	aca99b87bc	Fix config for tests 30	2019-11-16 22:22:30 +00:00
Matt Guthaus	69c5608b53	Allow gds to be written with supplies off. Fix extraction bug with new options.	2019-09-03 11:23:35 -07:00
jsowash	67c6cdf3bb	Fixed error where word_size was compared to num_words and added write_size to control_logic.py	2019-07-01 15:51:40 -07:00
Matt Guthaus	6e044b776f	Merge branch 'pep8_cleanup' into dev	2019-06-14 08:47:10 -07:00
mrg	bf86969972	Create sram subdirectory.	2019-05-31 08:56:24 -07:00