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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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499 Commits 5 Branches 63 Tags
0cc077598efc0eb7457c7150b5a53dcee052d712
Commit Graph
8 Commits
Author SHA1 Message Date
Michael Timothy Grimes 0cc077598e Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell. 2018-03-15 12:02:38 -07:00
Michael Timothy Grimes 65735c08e2 fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters 2018-03-08 16:39:26 -08:00
Michael Timothy Grimes 820a8440c9 adding unit test for bitcell array using pbitcell 2018-03-06 16:36:11 -08:00
Michael Timothy Grimes fc294cb282 Fixed cell height and width 2018-03-02 10:53:29 -08:00
Michael Timothy Grimes d33dec4e9e Separated add_globals function into add_ptx and add_globals 2018-03-02 10:49:26 -08:00
Michael Timothy Grimes d6ef91786b updating pbitcell with latest layout optimizations 2018-02-28 17:56:13 -08:00
Michael Timothy Grimes d41abb3074 moved pbitcell to new folder for parametrically sized cells 2018-02-28 11:25:22 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
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