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OpenRAM
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4,853 Commits 4 Branches 63 Tags 78 MiB
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5 Commits

Author SHA1 Message Date
mrg 7195d81736 Adjust WL and GND for contacted via2 spacing. 2022-04-19 10:32:37 -07:00
mrg 111533f0b0 Move power pins to horizontal or vertical layer in all cells. 2022-03-31 16:36:19 -07:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
ota2 8403749fec Add Q and Qbar labels 2021-02-27 18:27:08 -05:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00