5 Commits

Author	SHA1	Message	Date
Bugra Onal	3f1a5a2051	Shrunk address register in multibank verilog	2022-07-28 15:03:41 -07:00
Bugra Onal	5f45f7db15	Fixed the bad commas with post-process regex	2022-07-28 15:03:41 -07:00
Bugra Onal	29079bd6ac	Added conditional sections to template	2022-07-28 15:03:41 -07:00
Bugra Onal	24bb6f8c11	Multibank file generation (messy)	2022-07-28 15:03:37 -07:00
Bugra Onal	6d6063ef4e	modified template engine & sram multibank class	2022-07-21 15:56:29 -07:00