luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
748 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

7 Commits

Author SHA1 Message Date
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus 70c92c27ef Supply to M3 for bank select logic 2018-04-11 16:55:09 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00