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array_gen-to-dev
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Author SHA1 Message Date
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal a497943be3 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
Bugra Onal 874d965edb Template module done 2022-07-21 15:45:50 -07:00
Bugra Onal 99b517d55a Bank select 2022-07-21 15:45:50 -07:00
Bugra Onal 54a012b574 Templatable verilog file 2022-07-21 15:45:50 -07:00
mrg 0d616ae072 Merge branch 'dev' into stable 2022-07-21 09:37:24 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg 5ad97aa636 Update README and setpaths with new PYTHONPATH 2022-07-20 10:27:10 -07:00
mrg 3b0533c9c7 v1.2.0 2022-07-17 19:55:05 -07:00
mrg c406e2a9da Make macros use same DOCKER_CMD. 2022-07-13 17:19:25 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
Bugra Onal 6a4bd62206 Added unit test for multibank 2022-07-13 16:40:21 -07:00
Bugra Onal aada5a0d09 Not mathcing whitespace bug fixed 2022-07-13 16:38:22 -07:00
Bugra Onal e041b101a7 Fixed the bad commas with post-process regex 2022-07-13 16:37:47 -07:00
Bugra Onal 94f166e2d0 None check syntax fix 2022-07-13 16:36:14 -07:00
Bugra Onal 45d8c43376 write_size init in sram_config 2022-07-13 16:20:06 -07:00
Bugra Onal a38826f073 Fixed indent error on write_size init 2022-07-13 16:11:45 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
Bugra Onal 78d4e2aa8b Cleaned up tests dir after bad run 2022-07-08 17:03:53 -07:00
Bugra Onal 4028534a84 Fixed verilog filename double extension 2022-07-08 17:01:30 -07:00
Bugra Onal 289f48c3f3 Merge branch 'multibank' of github.com:VLSIDA/PrivateRAM into multibank 2022-07-08 14:23:05 -07:00
Bugra Onal 3647acda9e Fixed globals conflict 2022-07-08 14:17:51 -07:00
Bugra Onal a1645570a8 Replaced instances of addr_size with bank_addr 2022-07-08 13:55:02 -07:00
Bugra Onal 660226c192 Set write_size default to word_size 2022-07-08 13:54:56 -07:00
Bugra Onal 2c6d3223ea Added conditional sections to template 2022-07-08 13:51:07 -07:00
Bugra Onal 34f28554ad Multibank file generation (messy) 2022-07-08 13:51:07 -07:00
Bugra Onal 3b43cefdc5 modified template engine & sram multibank class 2022-07-08 13:51:07 -07:00
Bugra Onal 3805db072a Template section clone method 2022-07-08 13:51:07 -07:00
Bugra Onal a7db6d182e Template section clone method 2022-07-08 13:51:07 -07:00
Bugra Onal 5bbb8eae4c TEmplate rework 2022-07-08 13:51:07 -07:00
Bugra Onal 41d04f88f4 Base-verilog 2022-07-08 13:51:07 -07:00
Bugra Onal 4afa391a87 Base template additions 2022-07-08 13:51:07 -07:00
Bugra Onal e6ca67e945 Verilog Template additions 2022-07-08 13:51:07 -07:00
Bugra Onal 31bf5364ee Base verilog template init 2022-07-08 13:51:07 -07:00
Bugra Onal 16512bc4ee Template module done 2022-07-08 13:51:07 -07:00
Bugra Onal a69a016d9f Bank select 2022-07-08 13:51:07 -07:00
Bugra Onal 38a035a7da Templatable verilog file 2022-07-08 13:51:07 -07:00
mrg 58ea148d47 Add dlxtn latch for open reg file 2022-06-22 09:53:10 -07:00
mrg f7738c60a3 Don't install SRAM macros. 2022-06-21 13:53:08 -07:00
mrg ac86ad0e8a Move pdk installation inside docker to use Magic from docker image. 2022-06-21 12:10:15 -07:00
Jesse Cirimelli-Low 374562f354 rbc substrate issues 2022-06-16 15:17:07 -07:00
Bugra Onal 3ebb719535 Added conditional sections to template 2022-06-16 15:12:43 -07:00
mrg c479915c02 Update colenda with new device sizes. 2022-06-16 11:23:13 -07:00
mrg dc9ae6cd1a Increase column width in netgen LVS scripts 2022-06-16 10:30:58 -07:00