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Merged with dev, fixed config file conflict.

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Hunter Nichols
2018-11-05 14:58:52 -08:00
parent 4c26dede23 f3d1f7d55b
commit ff169fcb2b
3 changed files with 6 additions and 32 deletions
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compiler/example_config_freepdk45.py
-13
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@@ -9,16 +9,3 @@ temperatures = [25]
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
#Setting for multiport
# netlist_only = True
# num_rw_ports = 1
# num_r_ports = 1
# num_w_ports = 0
#Pbitcell modules for multiport
#bitcell = "pbitcell"
#replica_bitcell="replica_pbitcell"
#Custom 1rw+1r multiport cell. Set the above port numbers to rw = 1, r = 1, w = 0
# bitcell = "bitcell_1rw_1r"
# replica_bitcell = "replica_bitcell_1rw_1r"
compiler/example_config_scn4m_subm.py
+1 -14
View File
@@ -3,22 +3,9 @@ num_words = 16
tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [ 5.0 ]
supply_voltages = [ 3.3 ]
temperatures = [ 25 ]
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
#Setting for multiport
# netlist_only = True
# num_rw_ports = 1
# num_r_ports = 1
# num_w_ports = 0
#Pbitcell modules for multiport
#bitcell = "pbitcell"
#replica_bitcell="replica_pbitcell"
#Custom 1rw+1r multiport cell. Set the above port numbers to rw = 1, r = 1, w = 0
# bitcell = "bitcell_1rw_1r"
# replica_bitcell = "replica_bitcell_1rw_1r"