Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

compiler/tests/04_single_level_column_mux_pbitcell_test.py

@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class single_level_column_mux_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        
+        # check single level column mux in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+        
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
+        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_single_level_column_mux_test.py

@@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test):
         tx = factory.create(module_type="single_level_column_mux", tx_size=8)
         self.local_check(tx)
         
-        # check single level column mux in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
-        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
-
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -28,39 +28,39 @@ class hierarchical_decoder_test(openram_test):
 
         factory.reset()
         debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=16)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
 
         factory.reset()
         debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=17)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
         self.local_check(a)
 
         factory.reset()
         debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=23)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
         self.local_check(a)
 
         debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=32)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
         self.local_check(a)
 
         factory.reset()
         debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=65)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
         self.local_check(a)
 
         debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=128)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
         self.local_check(a)
 
         factory.reset()
         debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=341)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
         self.local_check(a)
 
         debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
-        a = factory.create(module_type="hierarchical_decoder", rows=512)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/06_hierarchical_decoder_test.py

@@ -20,47 +20,38 @@ class hierarchical_decoder_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        # Doesn't require hierarchical decoder
-        # debug.info(1, "Testing 4 row sample for hierarchical_decoder")
-        # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
-        # self.local_check(a)
-
-        # Doesn't require hierarchical decoder
-        # debug.info(1, "Testing 8 row sample for hierarchical_decoder")
-        # a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8)
-        # self.local_check(a)
 
         # check hierarchical decoder for single port
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=16)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
 
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=17)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
         self.local_check(a)
 
         debug.info(1, "Testing 23 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=23)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
         self.local_check(a)
 
         debug.info(1, "Testing 32 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=32)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
         self.local_check(a)
 
         debug.info(1, "Testing 65 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=65)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
         self.local_check(a)
 
         debug.info(1, "Testing 128 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=128)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
         self.local_check(a)
 
         debug.info(1, "Testing 341 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=341)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
         self.local_check(a)
 
         debug.info(1, "Testing 512 row sample for hierarchical_decoder")
-        a = factory.create(module_type="hierarchical_decoder", rows=512)
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
         self.local_check(a)
         
         globals.end_openram()

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode2x4_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 2x4 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode2x4")
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -26,16 +26,6 @@ class hierarchical_predecode2x4_test(openram_test):
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        # checking hierarchical precode 2x4 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode2x4")
-        self.local_check(a)
-        
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode3x8_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 3x8 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode3x8")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -26,16 +26,6 @@ class hierarchical_predecode3x8_test(openram_test):
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
         
-        # checking hierarchical precode 3x8 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode3x8")
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/18_port_data_1rw_1r_test.py

@@ -0,0 +1,78 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class port_data_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        from sram_config import sram_config
+
+        OPTS.bitcell = "bitcell_1w_1r"
+        OPTS.num_rw_ports = 0
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        c = sram_config(word_size=4,
+                        num_words=16)
+
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Eight way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/18_port_data_test.py

@@ -55,52 +55,6 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
         
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.num_rw_ports = 0
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-        
-        c.num_words=16
-        c.words_per_row=1
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "No column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
-        c.num_words=32
-        c.words_per_row=2
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Two way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.num_words=64
-        c.words_per_row=4
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Four way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.word_size=2
-        c.num_words=128
-        c.words_per_row=8
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Eight way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/30_openram_back_end_test.py

@@ -51,7 +51,7 @@ class openram_back_end_test(openram_test):
             debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage")
             exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
         else:
-            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
+            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
         config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
                                                                           out_file,
@@ -64,33 +64,32 @@ class openram_back_end_test(openram_test):
         
         # assert an error until we actually check a resul
         for extension in ["gds", "v", "lef", "sp"]:
-            filename = "{0}/{1}.{2}".format(out_path,out_file,extension)
-            debug.info(1,"Checking for file: " + filename)
-            self.assertEqual(os.path.exists(filename),True)
+            filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
+            debug.info(1, "Checking for file: " + filename)
+            self.assertEqual(os.path.exists(filename), True)
 
         # Make sure there is any .lib file
         import glob
         files = glob.glob('{0}/*.lib'.format(out_path))
         self.assertTrue(len(files)>0)
         
-        # Make sure there is any .html file 
+        # Make sure there is any .html file
         if os.path.exists(out_path):
             datasheets = glob.glob('{0}/*html'.format(out_path))
             self.assertTrue(len(datasheets)>0)
         
         # grep any errors from the output
-        output_log = open("{0}/output.log".format(out_path),"r")
+        output_log = open("{0}/output.log".format(out_path), "r")
         output = output_log.read()
         output_log.close()
-        self.assertEqual(len(re.findall('ERROR',output)),0)
-        self.assertEqual(len(re.findall('WARNING',output)),0)
-
+        self.assertEqual(len(re.findall('ERROR', output)), 0)
+        self.assertEqual(len(re.findall('WARNING', output)), 0)
 
         # now clean up the directory
         if OPTS.purge_temp:
             if os.path.exists(out_path):
                 shutil.rmtree(out_path, ignore_errors=True)
-            self.assertEqual(os.path.exists(out_path),False)
+            self.assertEqual(os.path.exists(out_path), False)
  
         globals.end_openram()
 

compiler/tests/30_openram_front_end_test.py

@@ -51,7 +51,7 @@ class openram_front_end_test(openram_test):
             debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage")
             exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
         else:
-            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
+            exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
         config_name = "{0}/tests/configs/config_front_end.py".format(OPENRAM_HOME)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
                                                                           out_file,
@@ -64,33 +64,32 @@ class openram_front_end_test(openram_test):
         
         # assert an error until we actually check a result
         for extension in ["v", "lef", "sp", "gds"]:
-            filename = "{0}/{1}.{2}".format(out_path,out_file,extension)
-            debug.info(1,"Checking for file: " + filename)
-            self.assertEqual(os.path.exists(filename),True)
+            filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
+            debug.info(1, "Checking for file: " + filename)
+            self.assertEqual(os.path.exists(filename), True)
 
         # Make sure there is any .lib file
         import glob
         files = glob.glob('{0}/*.lib'.format(out_path))
         self.assertTrue(len(files)>0)
         
-        # Make sure there is any .html file 
+        # Make sure there is any .html file
         if os.path.exists(out_path):
             datasheets = glob.glob('{0}/*html'.format(out_path))
             self.assertTrue(len(datasheets)>0)
         
         # grep any errors from the output
-        output_log = open("{0}/output.log".format(out_path),"r")
+        output_log = open("{0}/output.log".format(out_path), "r")
         output = output_log.read()
         output_log.close()
-        self.assertEqual(len(re.findall('ERROR',output)),0)
-        self.assertEqual(len(re.findall('WARNING',output)),0)
+        self.assertEqual(len(re.findall('ERROR', output)), 0)
+        self.assertEqual(len(re.findall('WARNING', output)), 0)
 
-
-       # now clean up the directory
+        # now clean up the directory
         if OPTS.purge_temp:
             if os.path.exists(out_path):
                 shutil.rmtree(out_path, ignore_errors=True)
-            self.assertEqual(os.path.exists(out_path),False)
+            self.assertEqual(os.path.exists(out_path), False)
 
         globals.end_openram()
 

compiler/tests/testutils.py

@@ -45,21 +45,34 @@ class openram_test(unittest.TestCase):
             a.gds_write(tempgds)
 
             import verify
-            result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
-            if result != 0:
+            # Run both DRC and LVS even if DRC might fail
+            # Magic can still extract despite DRC failing, so it might be ok in some techs
+            # if we ignore things like minimum metal area of pins
+            drc_result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
+
+            # Always run LVS if we are using magic
+            if "magic" in OPTS.drc_exe or drc_result == 0:
+                lvs_result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
+                
+            # Only allow DRC to fail and LVS to pass if we are using magic
+            if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0:
+                #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
+                #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
+                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
+                debug.warning("DRC failed but LVS passed: {}".format(a.name))
+            elif drc_result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
                 #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("DRC failed: {}".format(a.name))
-
-
-            result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
-            if result != 0:
+                
+            if lvs_result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
                 #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("LVS mismatch: {}".format(a.name))
 
+
         # For debug...
         #import pdb; pdb.set_trace()
         if OPTS.purge_temp: