port_data: Each submodule now specifies their bl/br names

before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <[email protected]>

compiler/pgates/single_level_column_mux.py

@@ -31,6 +31,12 @@ class single_level_column_mux(pgate.pgate):
         
         pgate.pgate.__init__(self, name)
 
+    def get_bl_names(self):
+        return "bl"
+
+    def get_br_names(self):
+        return "br"
+
     def create_netlist(self):
         self.add_modules()
         self.add_pins()