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port_data: Each submodule now specifies their bl/br names

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before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <[email protected]>
This commit is contained in:
Bastian Koppelmann
2020-02-12 15:00:50 +01:00
parent 64bf93e4e5
commit f9babcf666
8 changed files with 112 additions and 16 deletions
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compiler/modules/write_driver.py
+6
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@@ -37,6 +37,12 @@ class write_driver(design.design):
self.pin_map = write_driver.pin_map
self.add_pin_types(self.type_list)
def get_bl_names(self):
return "bl"
def get_br_names(self):
return "br"
def get_w_en_cin(self):
"""Get the relative capacitance of a single input"""
# This is approximated from SCMOS. It has roughly 5 3x transistor gates.