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port_data: Each submodule now specifies their bl/br names

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before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <[email protected]>
This commit is contained in:
Bastian Koppelmann
2020-02-12 15:00:50 +01:00
parent 64bf93e4e5
commit f9babcf666
8 changed files with 112 additions and 16 deletions
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compiler/modules/sense_amp_array.py
+14
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@@ -34,6 +34,20 @@ class sense_amp_array(design.design):
self.create_layout()
def get_bl_name(self, port=0):
bl_name = self.amp.get_bl_names()
if len(self.all_ports) == 1:
return bl_name
else:
return bl_name + "{}".format(port)
def get_br_name(self, port=0):
br_name = self.amp.get_br_names()
if len(self.all_ports) == 1:
return br_name
else:
return br_name + "{}".format(port)
def create_netlist(self):
self.add_modules()
self.add_pins()