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add nwell routing in bca

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This commit is contained in:
Jesse Cirimelli-Low
2023-08-21 20:12:36 -07:00
parent 5a6c78865d
commit f890160601
3 changed files with 37 additions and 48 deletions
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technology/sky130/custom/sky130_bitcell_array.py
+6 -6
View File
@@ -33,7 +33,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
self.add_supply_pins()
#self.add_supply_pins()
def add_modules(self):
""" Add the modules used in this design """
@@ -49,14 +49,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
""" Create the module instances used in this design """
self.all_inst={}
self.cell_inst={}
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True)] \
+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False)]\
+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True)] \
+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False)]
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \
+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False, mirror='MX')]\
+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False)] \
+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \
+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
bit_block = []
technology/sky130/custom/sky130_bitcell_base_array.py
+28 -38
View File
@@ -84,45 +84,35 @@ class sky130_bitcell_base_array(bitcell_base_array):
strap_pins = ["vdd", "gnd", "vdd"]
return strap_pins
def add_supply_pins(self):
""" Add the layout pins """
def route_supplies(self):
# Copy a vdd/gnd layout pin from every cell
print("routing power")
for inst in self.insts:
if "wlstrap" in inst.name:
if "VPWR" in inst.mod.pins:
self.copy_layout_pin(inst, "VPWR", "vdd")
if "VGND" in inst.mod.pins:
self.copy_layout_pin(inst, "VGND", "gnd")
if "VPWR" in inst.mod.pins:
self.copy_layout_pin(inst, "VPWR", "vdd")
if "VGND" in inst.mod.pins:
self.copy_layout_pin(inst, "VGND", "gnd")
for row in range(self.pattern.row_max+1):
inst = self.all_inst[row,0]
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
pin.width(),
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
try:
from openram.tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
self.objs.append(geometry.rectangle(layer["pwellp"],
pin.ll(),
pin.width(),
pin.height()))
except:
pin = inst.get_pin("vnb")
self.add_label("vdd", pin.layer, pin.center())
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
# if row == 2: #add only 1 label per col
#
# if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
# pin = inst.get_pin("vpb")
# self.objs.append(geometry.rectangle(layer["nwell"],
# pin.ll(),
# pin.width(),
# pin.height()))
# self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
#
# if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
# try:
# from openram.tech import layer_override
# if layer_override['VNB']:
# pin = inst.get_pin("vnb")
# self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
# self.objs.append(geometry.rectangle(layer["pwellp"],
# pin.ll(),
# pin.width(),
# pin.height()))
# except:
# pin = inst.get_pin("vnb")
# self.add_label("vdd", pin.layer, pin.center())