From f890160601f440b9a0311d544877a1645b5325de Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Mon, 21 Aug 2023 20:12:36 -0700 Subject: [PATCH] add nwell routing in bca --- compiler/modules/pattern.py | 7 +- .../sky130/custom/sky130_bitcell_array.py | 12 ++-- .../custom/sky130_bitcell_base_array.py | 66 ++++++++----------- 3 files changed, 37 insertions(+), 48 deletions(-) diff --git a/compiler/modules/pattern.py b/compiler/modules/pattern.py index af9d2e52..8b6070db 100644 --- a/compiler/modules/pattern.py +++ b/compiler/modules/pattern.py @@ -129,7 +129,6 @@ class pattern(): row_done = True continue if((self.bit_rows[col+dc] < self.num_rows) and (self.bit_cols[row+dr] < self.num_cols)): - print(row+dr, col+dc) if(inst.is_bitcell): #x_bit = sum(bit > 0 for bit in self.bit_rows) #y_bit = sum(bit > 0 for bit in self.bit_cols) @@ -170,11 +169,11 @@ class pattern(): def place_array(self): - (row_max, col_max) = list(self.parent_design.all_inst.keys())[-1] + (self.row_max, self.col_max) = list(self.parent_design.all_inst.keys())[-1] y = 0 - for row in range(row_max+1): + for row in range(self.row_max+1): x = 0 - for col in range(col_max+1): + for col in range(self.col_max+1): inst = self.parent_design.all_inst[row, col] self.place_inst(inst, (x, y)) x += inst.width diff --git a/technology/sky130/custom/sky130_bitcell_array.py b/technology/sky130/custom/sky130_bitcell_array.py index 4526374e..4c37fb11 100644 --- a/technology/sky130/custom/sky130_bitcell_array.py +++ b/technology/sky130/custom/sky130_bitcell_array.py @@ -33,7 +33,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): self.create_netlist() if not OPTS.netlist_only: self.create_layout() - self.add_supply_pins() + #self.add_supply_pins() def add_modules(self): """ Add the modules used in this design """ @@ -49,14 +49,14 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array): """ Create the module instances used in this design """ self.all_inst={} self.cell_inst={} - bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True)] \ - + [geometry.instance("01_strap", mod=self.strap, is_bitcell=False)]\ - + [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True)] \ - + [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False)] + bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \ + + [geometry.instance("01_strap", mod=self.strap, is_bitcell=False, mirror='MX')]\ + + [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \ + + [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')] bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \ + [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False)] \ - + [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \ + + [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \ + [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)] bit_block = [] diff --git a/technology/sky130/custom/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py index b1310a6a..07d187ed 100644 --- a/technology/sky130/custom/sky130_bitcell_base_array.py +++ b/technology/sky130/custom/sky130_bitcell_base_array.py @@ -84,45 +84,35 @@ class sky130_bitcell_base_array(bitcell_base_array): strap_pins = ["vdd", "gnd", "vdd"] return strap_pins - def add_supply_pins(self): - """ Add the layout pins """ + def route_supplies(self): # Copy a vdd/gnd layout pin from every cell - + print("routing power") for inst in self.insts: - if "wlstrap" in inst.name: - if "VPWR" in inst.mod.pins: - self.copy_layout_pin(inst, "VPWR", "vdd") - if "VGND" in inst.mod.pins: - self.copy_layout_pin(inst, "VGND", "gnd") + if "VPWR" in inst.mod.pins: + self.copy_layout_pin(inst, "VPWR", "vdd") + if "VGND" in inst.mod.pins: + self.copy_layout_pin(inst, "VGND", "gnd") + + for row in range(self.pattern.row_max+1): + inst = self.all_inst[row,0] + pin = inst.get_pin("vpb") + self.objs.append(geometry.rectangle(layer["nwell"], + pin.ll(), + pin.width(), + pin.height())) + self.objs.append(geometry.label("vdd", layer["nwell"], pin.center())) + + try: + from openram.tech import layer_override + if layer_override['VNB']: + pin = inst.get_pin("vnb") + self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) + self.objs.append(geometry.rectangle(layer["pwellp"], + pin.ll(), + pin.width(), + pin.height())) + except: + pin = inst.get_pin("vnb") + self.add_label("vdd", pin.layer, pin.center()) - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row, col] - for pin_name in ["vdd", "gnd"]: - self.copy_layout_pin(inst, pin_name) - # if row == 2: #add only 1 label per col - # - # if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins: - # pin = inst.get_pin("vpb") - # self.objs.append(geometry.rectangle(layer["nwell"], - # pin.ll(), - # pin.width(), - # pin.height())) - # self.objs.append(geometry.label("vdd", layer["nwell"], pin.center())) - # - # if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins: - # try: - # from openram.tech import layer_override - # if layer_override['VNB']: - # pin = inst.get_pin("vnb") - # self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center())) - # self.objs.append(geometry.rectangle(layer["pwellp"], - # pin.ll(), - # pin.width(), - # pin.height())) - # except: - # pin = inst.get_pin("vnb") - # self.add_label("vdd", pin.layer, pin.center()) - -