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fix capped array tests after dev merge

This commit is contained in:
samuelkcrow 2022-12-14 08:48:12 -08:00
parent 6a8a76dd23
commit f651b484c5
3 changed files with 32 additions and 30 deletions
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21
compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py
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@ -1,29 +1,29 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# See LICENSE for licensing information. # See LICENSE for licensing information.
# #
# Copyright (c) 2016-2021 Regents of the University of California # Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved. # All rights reserved.
# #
import sys, os
import unittest import unittest
from testutils import * from testutils import *
import sys, os
import globals import openram
from globals import OPTS from openram import debug
from sram_factory import factory from openram.sram_factory import factory
import debug from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test): class capped_bitcell_array_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell() openram.setup_bitcell()
debug.info(2, "Testing 4x4 array left and right replica for dp cell") debug.info(2, "Testing 4x4 array left and right replica for dp cell")
a = factory.create(module_type="capped_bitcell_array", a = factory.create(module_type="capped_bitcell_array",
@ -34,11 +34,12 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
right_rbl=[1]) right_rbl=[1])
self.local_check(a) self.local_check(a)
globals.end_openram() openram.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = openram.parse_args()
del sys.argv[1:] del sys.argv[1:]
header(__file__, OPTS.tech_name) header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner()) unittest.main(testRunner=debugTestRunner())

20
compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py
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@ -1,29 +1,29 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# See LICENSE for licensing information. # See LICENSE for licensing information.
# #
# Copyright (c) 2016-2021 Regents of the University of California # Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved. # All rights reserved.
# #
import sys, os
import unittest import unittest
from testutils import * from testutils import *
import sys, os
import globals import openram
from globals import OPTS from openram import debug
from sram_factory import factory from openram.sram_factory import factory
import debug from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test): class capped_bitcell_array_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell() openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell") debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="capped_bitcell_array", a = factory.create(module_type="capped_bitcell_array",
@ -33,11 +33,11 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
left_rbl=[0]) left_rbl=[0])
self.local_check(a) self.local_check(a)
globals.end_openram() openram.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = openram.parse_args()
del sys.argv[1:] del sys.argv[1:]
header(__file__, OPTS.tech_name) header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner()) unittest.main(testRunner=debugTestRunner())

21
compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py
View File

@ -1,29 +1,29 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# See LICENSE for licensing information. # See LICENSE for licensing information.
# #
# Copyright (c) 2016-2021 Regents of the University of California # Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
# All rights reserved. # All rights reserved.
# #
import sys, os
import unittest import unittest
from testutils import * from testutils import *
import sys, os
import globals import openram
from globals import OPTS from openram import debug
from sram_factory import factory from openram.sram_factory import factory
import debug from openram import OPTS
class capped_bitcell_array_1rw_1r_test(openram_test): class capped_bitcell_array_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell() openram.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for dp cell") debug.info(2, "Testing 4x4 non-replica array for dp cell")
a = factory.create(module_type="capped_bitcell_array", a = factory.create(module_type="capped_bitcell_array",
@ -32,11 +32,12 @@ class capped_bitcell_array_1rw_1r_test(openram_test):
rbl=[1, 1]) rbl=[1, 1])
self.local_check(a) self.local_check(a)
globals.end_openram() openram.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = openram.parse_args()
del sys.argv[1:] del sys.argv[1:]
header(__file__, OPTS.tech_name) header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner()) unittest.main(testRunner=debugTestRunner())