From f651b484c596de44052499738470728775033c6d Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 14 Dec 2022 08:48:12 -0800 Subject: [PATCH] fix capped array tests after dev merge --- ...apped_bitcell_array_bothrbl_1rw_1r_test.py | 21 ++++++++++--------- ...apped_bitcell_array_leftrbl_1rw_1r_test.py | 20 +++++++++--------- ..._capped_bitcell_array_norbl_1rw_1r_test.py | 21 ++++++++++--------- 3 files changed, 32 insertions(+), 30 deletions(-) diff --git a/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py index 29920124..1b860a64 100644 --- a/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_bitcell_array_bothrbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class capped_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 array left and right replica for dp cell") a = factory.create(module_type="capped_bitcell_array", @@ -34,11 +34,12 @@ class capped_bitcell_array_1rw_1r_test(openram_test): right_rbl=[1]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py index 3d414a33..de0d9177 100644 --- a/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_bitcell_array_leftrbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class capped_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 left replica array for dp cell") a = factory.create(module_type="capped_bitcell_array", @@ -33,11 +33,11 @@ class capped_bitcell_array_1rw_1r_test(openram_test): left_rbl=[0]) self.local_check(a) - globals.end_openram() + openram.end_openram() # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner()) diff --git a/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py index 7c4fd9bb..b2a8d97c 100644 --- a/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py +++ b/compiler/tests/14_capped_bitcell_array_norbl_1rw_1r_test.py @@ -1,29 +1,29 @@ #!/usr/bin/env python3 # See LICENSE for licensing information. # -# Copyright (c) 2016-2021 Regents of the University of California +# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz # All rights reserved. # +import sys, os import unittest from testutils import * -import sys, os -import globals -from globals import OPTS -from sram_factory import factory -import debug +import openram +from openram import debug +from openram.sram_factory import factory +from openram import OPTS class capped_bitcell_array_1rw_1r_test(openram_test): def runTest(self): config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) - globals.init_openram(config_file) + openram.init_openram(config_file, is_unit_test=True) OPTS.num_rw_ports = 1 OPTS.num_r_ports = 1 OPTS.num_w_ports = 0 - globals.setup_bitcell() + openram.setup_bitcell() debug.info(2, "Testing 4x4 non-replica array for dp cell") a = factory.create(module_type="capped_bitcell_array", @@ -32,11 +32,12 @@ class capped_bitcell_array_1rw_1r_test(openram_test): rbl=[1, 1]) self.local_check(a) - globals.end_openram() + openram.end_openram() + # run the test from the command line if __name__ == "__main__": - (OPTS, args) = globals.parse_args() + (OPTS, args) = openram.parse_args() del sys.argv[1:] header(__file__, OPTS.tech_name) unittest.main(testRunner=debugTestRunner())