Update riscv unit test

compiler/tests/50_riscv_func_test.py

@@ -22,13 +22,15 @@ class riscv_func_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        OPTS.analytical_delay = False
-        OPTS.netlist_only = True
-        OPTS.trim_netlist = False
+        
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
         globals.setup_bitcell()
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+        OPTS.local_array_size = 16
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/50_riscv_phys_test.py

@@ -28,8 +28,9 @@ class riscv_phys_test(openram_test):
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
         globals.setup_bitcell()
-        OPTS.route_supplies=False
-        OPTS.perimeter_pins=False
+        OPTS.route_supplies = False
+        OPTS.perimeter_pins = False
+        OPTS.local_array_size = 16
         
         c = sram_config(word_size=32,
                         write_size=8,