mirror of https://github.com/VLSIDA/OpenRAM.git
start of adding additional granularity to 1port col caps
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5ee3f4cc66
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@ -211,6 +211,13 @@ class cell_properties():
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self._col_cap_1port = _bitcell(["bl", "br", "vdd"],
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["OUTPUT", "OUTPUT", "POWER"])
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self._col_cap_1port_bitcell = _cell(["bl", "br", "vdd", "gnd"],
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["OUTPUT", "OUTPUT", "POWER", "GROUND"])
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self._col_cap_1port_strap = _cell(["vdd", "gnd"],
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["POWER", "GROUND"])
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self._row_cap_1port = _bitcell(["wl", "gnd"],
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["INPUT", "POWER", "GROUND"])
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@ -268,6 +275,14 @@ class cell_properties():
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def col_cap_1port(self):
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return self._col_cap_1port
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@property
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def col_cap_1port_bitcell(self):
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return self._col_cap_1port_bitcell
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@property
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def col_cap_1port_strap(self):
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return self._col_cap_1port_strap
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@property
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def row_cap_1port(self):
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return self._row_cap_1port
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@ -600,7 +600,7 @@ class VlsiLayout:
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shapes = self.getAllShapes(lpp)
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if len(shapes) != 1:
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debug.warning("More than one boundary found in cell: {}".format(structure))
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debug.warning("More than one or no boundaries found in cell: {}".format(structure))
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debug.check(len(shapes) != 0,
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"Error: "+str(structure)+".cell_size information not found yet")
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max_boundary = None
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