diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py
index 70fcc761..f8987339 100644
--- a/compiler/base/custom_cell_properties.py
+++ b/compiler/base/custom_cell_properties.py
@@ -211,6 +211,13 @@ class cell_properties():
         self._col_cap_1port = _bitcell(["bl", "br", "vdd"],
                                        ["OUTPUT", "OUTPUT", "POWER"])
 
+        self._col_cap_1port_bitcell = _cell(["bl", "br", "vdd", "gnd"],
+                                            ["OUTPUT", "OUTPUT", "POWER", "GROUND"])
+
+        self._col_cap_1port_strap = _cell(["vdd", "gnd"],
+                                          ["POWER", "GROUND"])
+
+
         self._row_cap_1port = _bitcell(["wl", "gnd"],
                                        ["INPUT", "POWER", "GROUND"])
 
@@ -268,6 +275,14 @@ class cell_properties():
     def col_cap_1port(self):
         return self._col_cap_1port
 
+    @property
+    def col_cap_1port_bitcell(self):
+        return self._col_cap_1port_bitcell
+
+    @property
+    def col_cap_1port_strap(self):
+        return self._col_cap_1port_strap
+
     @property
     def row_cap_1port(self):
         return self._row_cap_1port
diff --git a/compiler/gdsMill/gdsMill/vlsiLayout.py b/compiler/gdsMill/gdsMill/vlsiLayout.py
index 19018119..68e32762 100644
--- a/compiler/gdsMill/gdsMill/vlsiLayout.py
+++ b/compiler/gdsMill/gdsMill/vlsiLayout.py
@@ -600,7 +600,7 @@ class VlsiLayout:
 
         shapes = self.getAllShapes(lpp)
         if len(shapes) != 1:
-            debug.warning("More than one boundary found in cell: {}".format(structure))
+            debug.warning("More than one or no boundaries found in cell: {}".format(structure))
         debug.check(len(shapes) != 0,
                     "Error: "+str(structure)+".cell_size information not found yet")
         max_boundary = None