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start of adding additional granularity to 1port col caps

This commit is contained in:
jcirimel 2020-11-23 06:55:47 -08:00
parent 5ee3f4cc66
commit f40e5f6dba
2 changed files with 16 additions and 1 deletions
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15
compiler/base/custom_cell_properties.py
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@ -211,6 +211,13 @@ class cell_properties():
self._col_cap_1port = _bitcell(["bl", "br", "vdd"], self._col_cap_1port = _bitcell(["bl", "br", "vdd"],
["OUTPUT", "OUTPUT", "POWER"]) ["OUTPUT", "OUTPUT", "POWER"])
self._col_cap_1port_bitcell = _cell(["bl", "br", "vdd", "gnd"],
["OUTPUT", "OUTPUT", "POWER", "GROUND"])
self._col_cap_1port_strap = _cell(["vdd", "gnd"],
["POWER", "GROUND"])
self._row_cap_1port = _bitcell(["wl", "gnd"], self._row_cap_1port = _bitcell(["wl", "gnd"],
["INPUT", "POWER", "GROUND"]) ["INPUT", "POWER", "GROUND"])
@ -268,6 +275,14 @@ class cell_properties():
def col_cap_1port(self): def col_cap_1port(self):
return self._col_cap_1port return self._col_cap_1port
@property
def col_cap_1port_bitcell(self):
return self._col_cap_1port_bitcell
@property
def col_cap_1port_strap(self):
return self._col_cap_1port_strap
@property @property
def row_cap_1port(self): def row_cap_1port(self):
return self._row_cap_1port return self._row_cap_1port

2
compiler/gdsMill/gdsMill/vlsiLayout.py
View File

@ -600,7 +600,7 @@ class VlsiLayout:
shapes = self.getAllShapes(lpp) shapes = self.getAllShapes(lpp)
if len(shapes) != 1: if len(shapes) != 1:
debug.warning("More than one boundary found in cell: {}".format(structure)) debug.warning("More than one or no boundaries found in cell: {}".format(structure))
debug.check(len(shapes) != 0, debug.check(len(shapes) != 0,
"Error: "+str(structure)+".cell_size information not found yet") "Error: "+str(structure)+".cell_size information not found yet")
max_boundary = None max_boundary = None