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start of adding additional granularity to 1port col caps
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@@ -600,7 +600,7 @@ class VlsiLayout:
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shapes = self.getAllShapes(lpp)
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if len(shapes) != 1:
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debug.warning("More than one boundary found in cell: {}".format(structure))
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debug.warning("More than one or no boundaries found in cell: {}".format(structure))
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debug.check(len(shapes) != 0,
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"Error: "+str(structure)+".cell_size information not found yet")
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max_boundary = None
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