Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules.

compiler/options.py

@@ -50,8 +50,6 @@ class options(optparse.Values):
     analytical_delay = True
     # Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
     purge_temp = True
-    # Determines whether multi-port portion of unit tests are run or not
-    multiport_check = True
 
     # These are the configuration parameters
     num_rw_ports = 1

compiler/tests/04_precharge_test.py

@@ -18,22 +18,22 @@ class precharge_test(openram_test):
         import precharge
         import tech
         
+        # check precharge in single port
         debug.info(2, "Checking precharge for handmade bitcell")
         tx = precharge.precharge(name="precharge_driver", size=1)
         self.local_check(tx)
         
-        if OPTS.multiport_check:
+        # check precharge in multi-port
-            debug.info(2, "Checking precharge for pbitcell")
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
+        
+        debug.info(2, "Checking precharge for pbitcell (innermost connections)")
         tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(tx)
         
-            tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1")
+        debug.info(2, "Checking precharge for pbitcell (outermost connections)")
-            self.local_check(tx)
-            
         tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(tx)
 

compiler/tests/04_single_level_column_mux_test.py

@@ -20,22 +20,22 @@ class single_level_column_mux_test(openram_test):
         import single_level_column_mux
         import tech
         
+        # check single level column mux in single port
         debug.info(2, "Checking column mux")
         tx = single_level_column_mux.single_level_column_mux(tx_size=8)
         self.local_check(tx)
         
-        if OPTS.multiport_check:
+        # check single level column mux in multi-port
-            debug.info(2, "Checking column mux for pbitcell")
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
+        
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
         tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(tx)
         
-            tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-            self.local_check(tx)
-            
         tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(tx)
 

compiler/tests/06_hierarchical_decoder_test.py

@@ -28,6 +28,7 @@ class hierarchical_decoder_test(openram_test):
         # a = hierarchical_decoder.hierarchical_decoder(rows=8)
         # self.local_check(a)
 
+        # check hierarchical decoder for single port
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
         a = hierarchical_decoder.hierarchical_decoder(rows=16)
         self.local_check(a)
@@ -44,6 +45,28 @@ class hierarchical_decoder_test(openram_test):
         a = hierarchical_decoder.hierarchical_decoder(rows=512)
         self.local_check(a)
         
+        # check hierarchical decoder for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
+        a = hierarchical_decoder.hierarchical_decoder(rows=16)
+        self.local_check(a)
+
+        debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
+        a = hierarchical_decoder.hierarchical_decoder(rows=32)
+        self.local_check(a)
+
+        debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
+        a = hierarchical_decoder.hierarchical_decoder(rows=128)
+        self.local_check(a)
+
+        debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
+        a = hierarchical_decoder.hierarchical_decoder(rows=512)
+        self.local_check(a)
+
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -18,10 +18,21 @@ class hierarchical_predecode2x4_test(openram_test):
         import hierarchical_predecode2x4 as pre
         import tech
 
+        # checking hierarchical precode 2x4 for single port
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = pre.hierarchical_predecode2x4()
         self.local_check(a)
 
+        # checking hierarchical precode 2x4 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
+        a = pre.hierarchical_predecode2x4()
+        self.local_check(a)
+        
         globals.end_openram()
         
 # instantiate a copdsay of the class to actually run the test

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -18,10 +18,21 @@ class hierarchical_predecode3x8_test(openram_test):
         import hierarchical_predecode3x8 as pre
         import tech
 
+        # checking hierarchical precode 3x8 for single port
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = pre.hierarchical_predecode3x8()
         self.local_check(a)
         
+        # checking hierarchical precode 3x8 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
+        a = pre.hierarchical_predecode3x8()
+        self.local_check(a)
+
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/07_single_level_column_mux_array_test.py

@@ -16,6 +16,7 @@ class single_level_column_mux_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import single_level_column_mux_array
         
+        # check single level column mux array in single port
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8)
         self.local_check(a)
@@ -28,30 +29,25 @@ class single_level_column_mux_test(openram_test):
         a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4)
         self.local_check(a)
         
-        if OPTS.multiport_check:
+        # check single level column mux array in multi-port
-            debug.info(2, "Checking column mux array for pbitcell")
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
         
-            debug.info(1, "Testing sample for 2-way column_mux_array")
+        debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(a)
 
-            debug.info(1, "Testing sample for 4-way column_mux_array")
+        debug.info(1, "Testing sample for 4-way column_mux_array  in multi-port")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(a)
 
-            debug.info(1, "Testing sample for 8-way column_mux_array")
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (innermost connections)")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(a)
         
-            debug.info(1, "Testing sample for 8-way column_mux_array")
+        debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
-            a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
-            self.local_check(a)
-            
-            debug.info(1, "Testing sample for 8-way column_mux_array")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(a)
 

compiler/tests/08_precharge_array_test.py

@@ -18,23 +18,22 @@ class precharge_test(openram_test):
         import precharge_array
         import tech
 
+        # check precharge array in single port
         debug.info(2, "Checking 3 column precharge")
         pc = precharge_array.precharge_array(columns=3)
         self.local_check(pc)
         
-        if OPTS.multiport_check:
+        # check precharge array in multi-port
-            debug.info(2, "Checking precharge array for pbitcell")
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
         
+        debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
         pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(pc)
         
-            pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1")
+        debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
-            self.local_check(pc)
-            
         pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
         self.local_check(pc)
 

compiler/tests/08_wordline_driver_test.py

@@ -20,11 +20,12 @@ class wordline_driver_test(openram_test):
         import wordline_driver
         import tech
 
+        # check wordline driver for single port
         debug.info(2, "Checking driver")
         tx = wordline_driver.wordline_driver(rows=8)
         self.local_check(tx)
 
-        if OPTS.multiport_check:
+        # check wordline driver for multi-port
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0

compiler/tests/09_sense_amp_array_test.py

@@ -17,6 +17,7 @@ class sense_amp_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import sense_amp_array
 
+        # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
         self.local_check(a)
@@ -25,7 +26,7 @@ class sense_amp_test(openram_test):
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
         self.local_check(a)
         
-        if OPTS.multiport_check:
+        # check sense amp array for multi-port
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0

compiler/tests/10_write_driver_array_test.py

@@ -17,6 +17,7 @@ class write_driver_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import write_driver_array
 
+        # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
         a = write_driver_array.write_driver_array(columns=8, word_size=8)
         self.local_check(a)
@@ -25,7 +26,7 @@ class write_driver_test(openram_test):
         a = write_driver_array.write_driver_array(columns=16, word_size=8)
         self.local_check(a)
         
-        if OPTS.multiport_check:
+        # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0